Loop Filter Implementation

Loop filter is a low pass filter which exist inside a closed loop system(i.e. PLL)

 

Matlab code

 function [ lf_out ] = lfilt( lf_in )  
 % This is a simple loop filter code  
 persistent u1;  
 if isempty(u1)  
   u1=0;  
 end  
 tmp = lf_in + (u1 * 0.9375);  
 lf_out = u1;  
 u1 = tmp;  
 end  

Auto Generated VHDL code

 -- -------------------------------------------------------------  
 --   
 -- File Name: C:\Users\Berker\Desktop\fm_demod\matlab_sim\codegen\lfilt\hdlsrc\lfilt_FixPt.vhd  
 -- Created: 2016-02-19 15:41:54  
 --   
 -- Generated by MATLAB 8.1, MATLAB Coder 2.4 and HDL Coder 3.2  
 --   
 --   
 --   
 -- -------------------------------------------------------------  
 -- Rate and Clocking Details  
 -- -------------------------------------------------------------  
 -- Design base rate: 1  
 --   
 --   
 -- Clock Enable Sample Time  
 -- -------------------------------------------------------------  
 -- ce_out    1  
 -- -------------------------------------------------------------  
 --   
 --   
 -- Output Signal         Clock Enable Sample Time  
 -- -------------------------------------------------------------  
 -- lf_out            ce_out    1  
 -- -------------------------------------------------------------  
 --   
 -- -------------------------------------------------------------  
 -- -------------------------------------------------------------  
 --   
 -- Module: lfilt_FixPt  
 -- Source Path: lfilt_FixPt  
 -- Hierarchy Level: 0  
 --   
 -- -------------------------------------------------------------  
 LIBRARY IEEE;  
 USE IEEE.std_logic_1164.ALL;  
 USE IEEE.numeric_std.ALL;  
 ENTITY lfilt_FixPt IS  
  PORT( clk                :  IN  std_logic;  
     reset               :  IN  std_logic;  
     clk_enable            :  IN  std_logic;  
     lf_in               :  IN  std_logic_vector(13 DOWNTO 0); -- sfix14_En9  
     ce_out              :  OUT  std_logic;  
     lf_out              :  OUT  std_logic_vector(13 DOWNTO 0) -- sfix14_En11  
     );  
 END lfilt_FixPt;  
 ARCHITECTURE rtl OF lfilt_FixPt IS  
  -- Signals  
  SIGNAL enb               : std_logic;  
  SIGNAL lf_in_signed           : signed(13 DOWNTO 0); -- sfix14_En9  
  SIGNAL u1                : signed(13 DOWNTO 0); -- sfix14_En9  
  SIGNAL tmp               : signed(13 DOWNTO 0); -- sfix14_En9  
  SIGNAL tmp_1              : signed(13 DOWNTO 0); -- sfix14_En9  
  SIGNAL p2tmp_add_cast          : signed(28 DOWNTO 0); -- sfix29_En23  
  SIGNAL p2tmp_mul_temp          : signed(28 DOWNTO 0); -- sfix29_En23  
  SIGNAL p2tmp_add_cast_1         : signed(27 DOWNTO 0); -- sfix28_En23  
  SIGNAL p2tmp_add_cast_2         : signed(28 DOWNTO 0); -- sfix29_En23  
  SIGNAL p2tmp_add_temp          : signed(28 DOWNTO 0); -- sfix29_En23  
  SIGNAL tmp_2              : signed(13 DOWNTO 0); -- sfix14_En9  
  SIGNAL u1_1               : signed(13 DOWNTO 0); -- sfix14_En9  
  SIGNAL tmp_3              : signed(13 DOWNTO 0); -- sfix14_En9  
  SIGNAL lf_out_1             : signed(13 DOWNTO 0); -- sfix14_En11  
  SIGNAL lf_out_2             : signed(13 DOWNTO 0); -- sfix14_En11  
 BEGIN  
  lf_in_signed <= signed(lf_in);  
  enb <= clk_enable;  
  --spssa  
  --%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%  
  --                                     %  
  --    Generated by MATLAB 8.1, MATLAB Coder 2.4 and HDL Coder 3.2   %  
  --                                     %  
  --%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%  
  --UNT?TLED3 Summary of this function goes here  
  --  Detailed explanation goes here  
  tmp <= u1;  
  p2tmp_add_cast <= resize(lf_in_signed & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0', 29);  
  p2tmp_mul_temp <= tmp * to_signed(15360, 15);  
  p2tmp_add_cast_1 <= p2tmp_mul_temp(27 DOWNTO 0);  
  p2tmp_add_cast_2 <= resize(p2tmp_add_cast_1, 29);  
  p2tmp_add_temp <= p2tmp_add_cast + p2tmp_add_cast_2;  
  tmp_1 <= p2tmp_add_temp(27 DOWNTO 14);  
  tmp_2 <= tmp_1;  
  u1_1 <= tmp_2;  
  u1_reg_process : PROCESS (clk, reset)  
  BEGIN  
   IF reset = '1' THEN  
    u1 <= to_signed(0, 14);  
   ELSIF clk'EVENT AND clk = '1' THEN  
    IF enb = '1' THEN  
     u1 <= u1_1;  
    END IF;  
   END IF;  
  END PROCESS u1_reg_process;  
  tmp_3 <= u1;  
  lf_out_1 <= tmp_3(11 DOWNTO 0) & '0' & '0';  
  lf_out_2 <= lf_out_1;  
  lf_out <= std_logic_vector(lf_out_2);  
  ce_out <= clk_enable;  
 END rtl;  

RTL view

 Simulation

Matlab Test Bench Comparison

 for i=1:10  
 lfilt(1.95315)  
 end   
 ans =  
    0  
 ans =  
   1.9531  
 ans =  
   3.7842  
 ans =  
   5.5009  
 ans =  
   7.1102  
 ans =  
   8.6190  
 ans =  
   10.0334  
 ans =  
   11.3595  
 ans =  
   12.6027  
 ans =  
   13.7682