Nios2 Project(1)

Simple Nios2 Example Project

Software
Quartus2 - 13.0 S.P1
Nios2 13.0 Eclipse

STEP1)
In Quartus2 select Create a New Project.
You can specify also your fpga model.

STEP2) Quartus2: Tools -> Qsys

STEP3) There is only one core is named clk_0 as default.

STEP4) Add a Nios2 processor to the system.

STEP5) Then add a On chip Memory to the system.
This core has 3 ports.
->Clock input
->Reset input
->Avalon slave
Avalon is a communication standart and bus name of between the Microcontroller and a system peripheral. Peripheral slave will onnect to Nios2 master with this bus.
We select; RAM type, Auto block type, 32 bits, 8192 bytes.
Note1 : M4K is meaning 4,096 bits per clock. For ex: 4Kx1 or 128x36 memory.(e.g. Cyclone2)
             M9K is meanig 8,192 bits per clock. For ex: 8Kx1 or 256x36 memory.(e.g. Cyclone4)

Note2 : With this memory blocks, you can create special memories similar to FIFO,Shift Register, RAM or ROM. 


STEP6) Add a PIO core to the system. One bit output port is sufficent. Because, we'll only blink a led.

STEP7) Now, we can do connections between the peripherals.
             System menu -> Create Global Reset Network
             Connect the clock output of clock source to all peripheral's clock input pin.
             Nios2 Data Master should connect PIO and On Chip Memory Slave input.
             Nios2 Instruction Master should connect only On Chip Memory Slave input.
             You must select Reset and Exception address of Nios2 as On chip memory.
             Export external_connection port of PIO core and give a name it.
             System-> Assign Base Addresses
             At the end of the system connections should similar at the bottom figure.

STEP8) File->Save
             Generation -> Generate 
             In the HDL Example tab, you can see HDL instantiation example.

    component nios1_hw is
        port (
            reset_reset_n : in  std_logic := 'X'; -- reset_n
            clk_clk       : in  std_logic := 'X'; -- clk
            led_export    : out std_logic         -- export
        );
    end component nios1_hw;

    u0 : component nios1_hw
        port map (
            reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
            clk_clk       => CONNECTED_TO_clk_clk,       --   clk.clk
            led_export    => CONNECTED_TO_led_export     --   led.export
        );
 

STEP9)In this step i want to take your attention some important generated files.
.bsf :
.cmp :
.qsys: 
.sopcinf: 
Sentez dosyasının altında
.qip:

STEP10) Yeniden Quartus2 ye gidip block/schematic file ekliyoruz. Qsys de elde ettiğimiz sistemi şematik üzerinde instance ediyoruz. Ve IO bağlantılarını yapıyoruz. Ve .bdf dosyasını kaydediyoruz.

STEP11) Dosya sistemine Qsys de oluşturduğumuz .qip dosyasını ekliyoruz. .bdf i set as top level diyoruz.
Start Analysis&Synthesis
Pin planner

STEP12) Start Compilation